Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to ED0 to SDRAM to DDR SDRAM to SLDRAM, the latter of which is the subject of much current industry interest. SLDRAM has a high sustainable bandwidth, low latency, low power, user upgradability and support for large hierarchical memory applications. It also provides multiple independent banks, fast read/write bus turn-around, and the capability for small fully pipelined bursts.
An overview of SLDRAM devices can be found in the specification entitled “SLDRAM Architectural and Functional Overview,” by Gillingham, 1997 SLDRAM Consortium (Aug. 29, 1997), the disclosure of which is incorporated by reference herein.
Improvements in speed and memory density of SLDRAM and other contemporary memory devices have uncovered limitations in current schemes for addressing a specific memory device or a group of memory devices in a memory system, for example during calibration, testing, or READ and WRITE operations involving a single memory device. Such limitations include degradations in efficiency resulting from unnecessarily high power consumption.
For example, in order for one current memory system to complete an operation, such as a READ or WRITE operation, the memory controller may identify a particular memory device or a group of memory devices with which to perform the operation, encode the identification information in commands, and transmit the commands including the identification information to the device or group of devices. In one prior art system memory system, each individual device is assigned a unique ID code and each command contains an embedded ID code designating the intended recipient device(s) for that command. The memory controller then transmits every command to all devices in the system, and each device is required to capture and decode every command in order to determine whether the current command applies to that device. This scheme results in unnecessary power consumption and consequent loss of efficiency where high-speed data capture circuitry at each device is used to receive and decode commands irrelevant to that device.
Another selection scheme, used by SDRAM systems, does not allow for selection of an individual device but does allow for selection of a group of devices (e.g., all devices on a memory module) using designated chip-select lines connecting the memory controller to each group of devices in the system. Selection is accomplished by transmitting a chip select signal on the chip select lines, concurrently with or immediately before a command is transmitted on the command and address bus, by the memory controller, to each memory module associated with the group of memory devices to be selected. When a memory module receives a chip select signal, all memory devices on that module associated with the selected group capture and decode the command transmitted by the memory controller. For example, if two groups of devices coexist on one module, only those devices in the selected group may capture and decode the command. Because several memory devices are customarily associated with each group, this scheme does not allow selection of individual memory devices because a chip select signal line per device or other impractical solution would be needed.
The above-mentioned and other limitations in current device selection schemes created a need and desire for an improved scheme of selecting a particular memory device or group of devices for calibration or other operations, such as READ and WRITE operations.